A significant trend throughout IC development has been to reduce the size of the components within the IC's. As the size is reduced, the performance requirements and design margins of the components become more stringent. One aspect of IC's that affects the performance requirements and design margins is the interference between two components within the IC due to magnetic field generation by one or both of the components during operation of the IC. For example, an inductor formed on an IC chip can generate a relatively strong time-dependent magnetic field, which can induce current in other parts, or circuitry, of the IC, thereby affecting the performance of the other parts of the IC. Additionally, inductive coupling between the inductor and other parts of the IC, such as the substrate of the IC, can reduce the quality of the inductor, thereby affecting the performance of the inductor.
A typical on-chip inductor 100 formed on an IC 102 is shown in FIGS. 1 and 2. The inductor 100 is generally spiral-shaped, as seen in the top view in FIG. 2. Additionally, the inductor 100 is typically located in one interconnect layer (a.k.a. “metal layers” and “conductor layers”) of the IC 102, such as the top interconnect layer 104. The inductor 100 is, thus, generally formed by latitudinal and longitudinal conductors 106 within the top interconnect layer 104. The IC 102 also generally includes via layers and other interconnect layers 108, a contact layer 110 and a substrate 112 (FIG. 1). The substrate 112 generally includes various structures and components, such as transistors, capacitors, etc. (not shown). The inductor 100 is typically connected through the via layers and other interconnect layers 108 and the contact layer 110 to the substrate 112 by conductors 114 and 116 (FIG. 1) that contact the inductor 100 at points 118 and 120 (FIG. 2).
Upon operation of the IC 102, a transverse magnetic field, represented by magnetic flux lines 122 (FIG. 1), is generated by the inductor 100. The magnetic flux lines 122 extend through the via layers and other interconnect layers 108, the contact layer 110 and the substrate 112. As the magnetic field varies, currents are induced in the substrate 112. Though the magnetic field is stronger nearer to the inductor 100, as indicated by the density of the magnetic flux lines 122, the magnetic field is still relatively strong down in the substrate 112. Thus, if the inductance of the inductor 100 is relatively high, the effect of the magnetic field on the substrate 112 may be significant.
There are several options for countering the effects of the magnetic field of the inductor 100 on the other components of the IC 102. One option is to include a ground plate (not shown) or a guard ring 124 (FIG. 1) in the IC 102 to effectively “absorb” some of the magnetic field, thereby reducing the intensity of the magnetic field in the substrate 112. The ground plate (typically polysilicon or metal) would typically be between the contact layer 110 and substrate 112 transversing the magnetic field area. The guard ring 124 is typically in the substrate 112 below the front end layers (not shown). The guard ring 124 is typically a highly doped grounded region that is deeper than a well region. This option, however, takes up valuable space within the IC 102 and increases the cost of the IC 102.
Another option is to locate the other components of the IC 102 in the substrate 112 at a sufficient distance from the inductor 100 that the magnetic field is too weak to have any significant effect on the performance of the other components. Thus, a region beneath the inductor 100 is free of any of the other components. This option, however, may waste valuable space in the IC 102 and require conductor lines between components to be undesirably long to reach between opposite sides of the inductor 100. In fact, in some applications, the inductors may take up a significant percentage of the area of the IC, resulting in significantly fewer IC's per wafer if the other components cannot be placed close to the inductors.
Another option is to allow for sufficient margins in the design of the other components of the IC 102. This option, however, results in a lower-performing IC.
Another option is to make the design of the inductor 100 more aggressive with lesser margins. This option, however, results in a more expensive IC.
Another option is to make the inductors larger to compensate for smaller quality factors. This option, however, may result in taking up a significant percentage of the IC's area with the inductors, increasing the size of the IC's and reducing the number of IC's per wafer.
It is with respect to these and other considerations that the present invention has evolved.